Interrupts

The host bus has one interrupt line available from the TSync Time Code Processor. All interrupt sources destined for the host bus are multiplexed on the single interrupt line. All interrupts are masked on startup, but can be unmasked using the host bus interrupt mask register. Whether an interrupt is masked or not, the current state of the interrupt is available by reading the Host Bus Interrupt Status register. All interrupt sources are latched based on an edge transition. All interrupts are cleared in the host bus interrupt status register.

Interrupt Descriptions

1PPS Received

This interrupt is driven on the incident edge of the PPS.

Timing System Service Request

This interrupt is used by the micro to request attention from the local bus.

Local/μC Bus FIFO Empty

This interrupt is driven when the FIFO from the local bus to the microcontroller bus becomes empty. It is based on the rising edge of the FIFO’s empty flag.

Local/μC Bus FIFO Overflow

This interrupt is driven when the FIFO from the local bus to the microcontroller bus is overflowed. It is based on the rising edge of the FIFO’s overflow flag.

μC/local bus FIFO Data Available

This interrupt is driven when the FIFO from the microcontroller bus to the local bus is no longer empty. It is based on the falling edge of the FIFO’s empty flag.

μC/local bus FIFO Overflow

This interrupt is driven when the FIFO from the microcontroller bus to the local bus is overflowed. It is based on the rising edge of the FIFO’s overflow flag.

GPIO Input x Event

This interrupt is driven when the active edge of the GPIO input signal is received.

GPIO Output x Event

The interrupt is driven when an event occurs in the GPIO output. An event depends on the mode of operation of the GPIO output. In Direct mode, an event is triggered when the output Value in the GPIO output control / status register is changed and creates the active edge selected by the GPIO direct mode output interrupt active edge bit in that same register. This can be used to generate a “software” interrupt by setting the GPIO output appropriately. In match time mode, an interrupt is generated whenever the GPIO output high match time or GPIO output low match time registers are enabled and subsequently matched against the current system time. In square wave mode, an interrupt is generated whenever the GPIO output generates the active edge as selected by the GPIO output square wave active edge bit in the GPIO output control / status register. This can be used to generate a periodic interrupt at the rate of the square wave.

Time Stamp Data Available

This interrupt is driven when the time stamp FIFO goes non-empty. Time stamp data is available in the time stamp FIFO when this interrupt occurs.